Project Title: Conquering MPSoC Complexity with Principles of a Self-Aware Information Processing Factory
Host: Univ. of California, Irvine, Center for Embedded & Cyber-physical Systems, Irvine, CA, USA.
Supervisor/Contact Person: Prof. Fadi Kurdahi (Kurdahi@uci.edu)
Co-supervisor: Prof. Nikil Dutt (email@example.com).
Postdoc: PhD degree in CS, Computer Engineering or EE from a top University.
PhD: Master’s in Computer Science, Computer Engineering or equivalent from a top University
Develop and evaluate hardware-assisted runtime verification models, architectures and tools.
Develop evaluate machine learning-based specification mining methods and tools.
Familiarity with hardware-assisted runtime verification formalism, tools and methods
Familiarity with machine-learning algorithms
Familiarity with specification mining methods and applications.
Experience with FPGA tools
Experience with multiprocessor simulators such as GEM5.
Planned visits and collaboration:
TU Munich (Professor Andreas Herkersdorf)
TU Branschweig (Professor Rolf Ernst)
Ideally, candidates would be able to start in Winter or Spring 2018 for a period of 1 year with possibility of extension up to 3 years total.
To Inquire: Please send a CV to Fadi Kurdahi (firstname.lastname@example.org).
Nikil Dutt, Fadi J. Kurdahi, Rolf Ernst, and Andreas Herkersdorf. 2016. Conquering MPSoC complexity with principles of a self-aware information processing factory. In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES ’16). ACM, New York, NY, USA, Article 37, 4 pages. DOI: https://doi.org/10.1145/2968456.2973275].
Ahmed Nassar, Fadi J. Kurdahi, and Wael Elsharkasy. 2015. NUVA: architectural support for runtime verification of parametric specifications over multicores. In Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES ’15). IEEE Press, Piscataway, NJ, USA, 137-146.
A. Nassar, F. J. Kurdahi and S. R. Zantout, “Topaz: Mining high-level safety properties from logic simulation traces,” 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016, pp. 1473-1476