Job title : Research engineer
Department : Embedded systems
Type of contract : Limited duration contract of 18 months (CDD)
Place : Toulouse, France (IRT Saint Exupéry)
Salary depending on past experience (minimum gross salary is 3.000
euros per month, which includes health coverage, unemployment, and
retirement).
1. Context, role and responsibilities
The CAPHCA research project (Critical Applications on Predictable
High-Performance Computing Architectures) conducted within the
Saint-Exupery IRT in Toulouse aims at defining and implementing a
complete framework for the design of safe multi-core architectures
with a high performance level.
This project gathers several industries from the avionics and
automotive domains, third party suppliers for hardware simulation
platforms, and research laboratories in the area of formal methods,
programming languages, and real-time embedded systems. The duration of
the project is 4 years, up to April 2020.
The proposed job focuses on improving the determinism of multi-core
platforms, both at the hardware and software level. The applicant will
join a team consisting of beginner and experienced engineers, in the
field of real-time embedded systems. The job includes writing research
papers and giving presentations at international conferences.
The work program includes two research axes, a main one (a single-core
execution platform) and a secondary one (multi-core extension), both
centered on the determinism issues.
2. Main axis: design and implementation of a deterministic execution platform (12 to 24 months)
The goal of this first research axis is to assess the PRecision TImed
approach (PRET [1]) on an industrial case study:
– Evaluation and selection of a PRET platform (from UC Berkeley or from Uni. Auckland).
– Implementation of the chosen platform:
+ Implementation of the platform based on the existing results;
integration of the required hardware components for the industrial case study.
+ Implementation of the ForeC compiler and programming IDE [2].
As most as possible, this work will reuse the existing results, in order
to put the emphasis on the particularities of the industrial case study.
– Implementation of the case study itself (design and programming in ForeC).
– Performance evaluation of the platform (response time, determinism,
…) and comparative study with other existing COTS platforms (e.g.,
Infineon Aurix, XMOS X1, …).
– Assessment of the adequacy of the proposed platform to the
industrial needs.
– Contribution to a state of the art paper for the design of
deterministic execution platforms and the use of reactive
programming languages for multi-core platforms.
– If time allows: porting the ForeC toolchain on a standard automotive
platform (such as Autosar for Aurix).
[1] Stephen Edwards and Edward A. Lee. UC Berkeley Technical Report
No. UCB/EECS-2006-149. “The Case for the Precision Timed (PRET)
Machine.” November 2006.
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-149.html.
[2] Eugene Yip, Partha S. Roop, Alain Girault, and Morteza
Biglari-Abhari. “Synchronous Deterministic Parallel Programming
for Multicores with ForeC: Programming Language, Semantics, and
Code Generation.” Inria research report RR-8943. September 2016.
https://hal.archives-ouvertes.fr/INRIA/hal-01351552v1
3. Secondary axis: Implementation of a deterministic multi-core execution platform (4-6 months)
The goal of this second research axis is to evaluate a novel many-core
architecture aiming at temporal determinism.
– Design, implementation, and assessment of a case study many-core
micro-architecture on a Xilinx FPGA.
– Contribution to a state of the art paper on many-core platforms.
4. Other activities
The applicant will also contribute to the other regular duties related to the CAPHCA project:
– Contributing to writing the project deliverables and to the meetings.
– Technical discussions with the other project members.
Background and past experience
The applicant should hold a PhD in one of the following areas:
– Synchronous programming languages (Lustre, Esterel, …)
– Multi-core architectures
– MPSoC architecture
– WCET analysis (Worst-Case Execution Time)
Beginners or postdocs with limited experience are welcome.
Contacts
Please send your CV, motivation letter, and the names of two
references to:
– Eric Jenn <eric.jenn@irt-saintexupery.com>
– Alain Girault <alain.girault@inria.fr>
